Field of the Invention
The present invention relates to an array substrate for a display device, and more particularly, to an array substrate for a display device including a shorting bar to prevent defects due to static electricity and a method of manufacturing the same.
Discussion of the Prior Art
Generally, a liquid crystal display device is operated using optical anisotropy and polarization of liquid crystal. Molecules of the liquid crystal have a thin and long structure and have a directional alignment, and when applying electric field to the molecules, the alignment of the molecules can be controlled.
In other words, when the alignment direction of the liquid crystal molecules is changed using an electric field, light is refracted in the aligned direction due to the optical anisotropy and thus images can be displayed.
The liquid crystal display device is manufactured by a TFT process of forming a gate line, a data line, a thin film transistor (TFT) and a pixel electrode on an array substrate, and forming a black matrix, a color filter and a common electrode on a color filter substrate, a cell process of injecting a liquid crystal between the array substrate and the color filter substrate, cutting in cell unit, and forming a unit panel, and a module process of attaching a driving IC and a printed circuit board (PCB) to the unit panel, and assembling it with a backlight unit.
The plural array substrates can be in a large-sized substrate referred to as a mother glass or an array mother glass.
Static electricity may occur when manufacturing the mother glass and cause fatal adverse effects on elements formed at the array substrate.
For example, when an insulating layer between two conductive lines is electrically broken down by strong static electricity, the two conductive lines are short-circuited and thus the liquid crystal display device is not normally operated.
To prevent the short circuit and degradation of the elements due to the static electricity, a shorting bar is formed at a peripheral portion of the mother glass and at a non-display region of each cell, which is explained as follows.
FIG. 1 is a view illustrating the prior art mother glass, and FIG. 2 is a view enlarging a region A of FIG. 1.
Referring to FIGS. 1 and 2, a mother glass 10 includes a plurality of cell areas CA, each of which corresponds to an array substrate of a unit cell to be formed through post-processes.
Size of each of the plurality of cell areas CA may be changed depending on size of the liquid crystal display device. FIG. 1 shows an example that 32 cells are formed in one mother glass 10.
A shorting bar 20 is formed on the mother glass 10, and each shorting bar 20 includes a plurality of horizontal portions each formed at a boundary portion between adjacent row lines of cell areas CA, and an edge portion connecting the plurality of horizontal portions and surrounding a peripheral portion of the whole of the cell areas CA.
Each cell area CA includes a non-display area NDA and a display area DA, and the non-display area NDA includes a FPC (flexible printed circuit) pad portion 30 and a DIC (driving integrated circuit) pad portion 40.
The display portion DA may include a plurality of gate lines 70, a plurality of data lines 80 and electrical elements such as a plurality of thin film transistors.
A plurality of third pads 32 are formed in the FPC pad portion 30, and a plurality of first pads 42, and a plurality of second pads 44 are formed in the DIC pad portion 40.
The third pads 32 of the FPC pad portion 30 are portions to which a flexible printed circuit (FPC) board is attached in a later module process, and are electrically connected to the shorting bar 20 through a plurality of third link lines 25.
The first pads 42 and the second pads 44 of the DIC pad portion 40 are portions to which a data driving integrated circuit (IC) is attached in a later module process, and particularly, the data driving IC may be mounted in a COG (chip on glass) manner the data driving IC is directly connected to the array substrate. The first pads 42 are connected to the third pads 32 through first link lines 35.
The data driving IC functions to supply image data voltages to the display area (DA) according to a timing signal and image data signal from the outside, and in some cases, the data driving IC may generate a timing signal therein other than the timing signal from the outside and generate or supply a gate driving signal.
The second pads 44 are connected to the display area DA through a plurality of second link lines 45, and may function to transfer the image data voltage from the data driving IC to the display area DA.
The shorting bar 20 is formed to have a width much greater than other signal lines. Accordingly, the shorting bar 20 may function as a reservoir of charges, and charges generated by static electricity in the array substrate in processes of manufacturing the array substrate is transferred to the shorting bar 20 and discharged to an external apparatus stage or the like.
However, even though the shorting bar 20 is configured, internal circuit is prone to be damaged because of static electricity occurring in the cell process.
Particularly, when coating an alignment layer on the array substrate and conducting a rubbing process, static electricity is prone to occur because of direct friction between a rubbing cloth and signal line/pad portion on the non-display area NDA where the alignment layer is not coated. Accordingly, damage to circuit portion occurs because of movement of charge inside the display area DA.
Particularly, in case of the COG type driving IC, the DIC pad portion 40 is separately configured and thus moving path of current is complicated. Accordingly, the prior art shorting bar 20 is insufficiently to completely restrain defect occurrence due to static electricity.